In conventional arithmetic processing units, such as processors, high-speed cache memories running at a higher speed than the main memory units are installed in order to speed up processes. In some cases, the cache memories include instruction cache memories that hold instructions and operand cache memories that hold operands as dedicated cache memories.
Cache tags (TAG) are used to search for instruction caches and operand caches. For these cache tags, static random access memories (SRAM) that are random access memories (RAM) containing memory elements made up of transistors are usually used.
To reduce electrical power consumption of the cache tags, various technologies are known. For example, there is a known technology for reducing electrical power consumption by reducing the operations performed on an address array when an address of a cache memory being referred to is an address contiguous to the previous cache memory reference address that was referred to, and these addresses are in the same cache line (see Japanese Laid-open Patent Publication No. 11-184752). There is also another known technology for reducing electrical power consumption by using an SRAM cell made up of a transistor, as memory elements of a TAG memory and a DATA memory that constitute a cache memory (see Japanese Laid-open Patent Publication No. 07-134701). Furthermore, there is also another known technology for reducing electrical power consumption by using a DRAM as a cache data memory (see Japanese Laid-open Patent Publication No. 07-200404).
With the conventional technology, if a TAG memory is referred to, even when the same address as the one previously referred to is referred to again, a value is obtained again from the memory element of the TAG memory. Because the TAG memory is made up of an SRAM, electrical power is consumed every time a reading is performed by referring to the memory element of the SRAM. In an address decoder constituted of a dynamic circuit or a read path that uses a dynamic circuit, even when the same value is read from the same previously read address, pre charged electrical power is consumed because a dynamic circuit is used.
However, it is undesirable to consume electrical power at least when the same value is read from the same address. Furthermore, it is also desirable to reduce the electrical power consumption when the same value is read even though addresses are different. Furthermore, it is preferable that the electrical power consumption be reduced when a similar value is read even though a different value is read from a different address.
However, with the conventional technology for using an SRAM as a cache tag memory, there is a problem in that a large amount of electrical power is consumed when a value is read even when the same value or a similar value is read.